The present invention relates to a plasma display apparatus and a method of manufacturing the same. More particularly, the present invention relates to a plasma display apparatus equipped with a power recovery circuit in a sustaining circuit that reduces power consumption, a method of driving a plasma panel display employing the ALIS (Alternate Lighting of Surfaces) system, in which plural first and second electrodes are arranged adjacently and display lines are formed between every pair of adjacent electrodes, and a plasma display apparatus employing the same.
The plasma display panel (PDP) has good visibility because it generates its own light, is thin and can be made with large and high-speed display, therefore, it is attracting interest as a replacement for the CRT display. Since the structure of a typical PDP has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. 7-160219, Japanese Unexamined Patent Publication (Kokai) No. 9-160525, and Japanese Unexamined Patent Publication (Kokai) No. 9-325735, a detailed explanation is omitted here and, instead, only points relating directly to the present invention are explained.
FIG. 1 is a block diagram showing a total structure of a general PDP apparatus. In a PDP 10, n X electrodes 11 and Y electrodes 12 are arranged in adjacent and alternating parallel relationships, forming n pairs, each pair of an X electrode 11 and a Y electrode 12, and light is emitted for display between the X electrode 11 and Y electrode 12 of each pair. Y electrodes and X electrodes are called display electrodes and are also called sustaining electrodes. Address electrodes 13 are provided in the direction that runs at a right angle to the direction in which the display electrodes extend, and display cells are formed at crossings of the address electrodes and pairs of X electrode 11 and Y electrode 12.
The Y electrodes 12 are connected to a scan driver 14. The scan driver 14 is equipped with switches 16, the number of which being equal to that of the Y electrodes, and the switches are switched so that scan pulses from a scan signal generating circuit 15 are applied sequentially during the address period, and sustaining pulses from a Y sustaining circuit 19 are applied simultaneously during the sustaining discharge period. The X electrodes 11 are connected commonly to an X sustaining circuit 18, and the address electrodes 13 are connected to an address driver circuit 17. In an image signal processing circuit 21, image signals are converted so as suit the operation in the PDP apparatus, and are then supplied to the address driver circuit 17. A drive control circuit 20 generates and supplies signals that control each part of the PDP apparatus.
FIG. 2 is a time chart showing drive signals of the PDP apparatus. In the PDP apparatus, a display frame is refreshed at predetermined intervals, and a display period is called a field. In order to realize a gray scale, a field is divided into plural subfields and the subfields that emit light are selected for each display cell. Each subfield consists of the reset period during which all display cells are initialized, the address period during which all display cells are put into the status corresponding to the display image, and the sustaining discharge period during which each display cell emits light according to the set status. During the sustaining discharge period, sustaining pulses are applied to X electrodes and Y electrodes alternately and sustaining discharges are performed in the display cell specified to emit light during the address period, resulting in light emission for display.
In the PDP apparatus, it is necessary to apply a voltage of about 200 V at maximum between electrodes as a high frequency pulse during the sustaining discharge period, and the width of a pulse is a few microseconds in a system in which the gray scale is realized by the representation of subfields. Since such a high voltage and a high frequency signal are required to drive a PDP, the power consumption of a general PDP apparatus is large and reduction in power consumption is demanded. In U.S. Pat. No. 4,070,663, the control method to suppress the power consumption of the capacitive display unit such as an EL (Electro-Luminescence) apparatus, in which an inductor device is provided to form a resonant circuit with the capacitor of the display unit, has been disclosed. In addition, the sustaining discharge driver and the address driver for the PDP panel equipped with a power recovery circuit consisting of inductor devices have been disclosed in U.S. Pat. No. 4,866,349 and U.S. Pat. No. 5,081,400. Moreover, in Japanese Unexamined Patent Publication (Kokai) No. 7-160219, the construction of a three-electrode type display unit equipped with two inductors provided to the Y electrode, one of which forms a recovery circuit to recover the applied power while the Y electrode is switched from a high voltage state to a low voltage state, and the other inductor forms an application path to apply the accumulated power while the Y electrode is switched from a low voltage state to a high voltage state.
FIG. 3 is a schematic showing an example of a typical construction of a sustaining circuit equipped with a power recovery circuit, in which a recovery circuit to recover power and an application circuit to apply the accumulated power is separated. Circuits to generate signals V1 to V4 are also provided, but they are omitted here. Reference code Cp refers to a drive capacitance of a display cell, formed by the X electrode and Y electrode of a PDP. Though a sustaining circuit of one of the electrodes is shown here, the other electrode is also connected to a similar sustaining circuit. In the circuit in FIG. 3, the part consisting of output devices (transistors) 31 and 33, and drive circuits 32 and 34 is a sustaining circuit without a power recovery circuit, and the part consisting of output devices (transistors) 37 and 40, drive circuits 38 and 41, inductance devices 35 and 43, capacitor 39, and diodes 36 and 42, is a power recovery circuit. The signals V1 and V2 are supplied to the drive circuits 32 and 34, respectively, and the signals VG1 and VG2 output therefrom are supplied to the gates of the output devices (transistors) 31 and 33. When the signal V1 is “High (H)”, the output device 31 turns on and an H level signal is applied to the electrode. At this time, the signal V2 is “Low (L)”, and the output device 33 is off. Immediately after the signal V1 turns to L and the output device 31 turns off, the signal V2 turns to H and the output device 33 turns on, and the ground level is applied to the electrode.
In the sustaining circuit with the power recovery circuit, when sustaining pulses are applied, before the signal V1 turns to H the signal V2 turns to L, and after the output device 33 turns off the signal V3 turns to H, the output device 40 turns on, a resonant circuit is formed by the capacitor 39, diode 42, inductor 43, and capacitor Cp, and the power accumulated in the capacitor 39 is supplied to the electrode, causing the potential of the electrode to rise. Just before the increase of the potential is completed, the signal V3 turns to L and the output device 40 turns off, then the signal V1 turns to H and the output device 31 turns off, thus the potential of the electrode is fixed to Vs. When the application of sustaining pulses is terminated, the signal V1 turns to L first and after the output device 31 turns off, the signal V4 turns to H, the output device 37 turns on, and a resonant circuit is formed by the capacitor 39, diode 36, inductor 35, and capacitor Cp, and the power accumulated in the capacitor Cp is supplied to the capacitor 39, thus the voltage of the capacitor 39 is raised. Therefore, the power accumulated in the capacitor Cp is recovered to the capacitor 39 by the sustaining pulses applied to the electrode. Just before the reduction in potential of the electrode is completed, the signal V4 turns to L, the output device 37 turns off, then the signal V2 turns to H, the output device 33 turns on, and the potential of the electrode is fixed to the ground level. During the sustaining discharge period, the above-mentioned operation is repeated a number of times equal to that of the sustaining pulses. In the structure mentioned above, the power consumption caused by the sustaining discharge can be suppressed.
On the other hand, a higher precision of the display is required for the PDP apparatus, and the system in which light is emitted for display between every adjacent display electrode has been disclosed in Japanese Patent No. 2801893. This system is called the ALIS system and is called the same here. Since the detail of the structure of the ALIS system has been disclosed in Japanese Patent No. 2801893, only the points relating to the present invention are explained here.
FIG. 4 is a general block diagram of a PDP employing the ALIS system. As shown schematically, in the PDP employing the ALIS system, n Y electrodes (second electrodes) 12-O and 12-E and n+1 X electrodes (first electrodes) 11-O and 11-E are arranged adjacently by turns and light is emitted between every adjacent display electrode (Y electrode and X electrode). Therefore, 2n+1 display electrodes form 2n display lines. This means that the precision can be doubled with the same number of the display electrodes as that in FIG. 1, in the ALIS system. The ALIS system is also characterized by a high luminance because the discharge space can be used efficiently without any waste and a high opening ratio can be obtained to give a small loss of light due to electrodes or the like. Light is emitted between every adjacent display electrode for display in the ALIS system, but it is impossible to cause all discharges to occur at the same time. Therefore, so-called interlaced scanning, in which odd-numbered lines and even-numbered lines are used in a time-shared manner for display, is employed. In the odd field, odd-numbered display lines are used for display, and even-numbered display lines are used for display in the even field, and the display combining the odd field and the even field is obtained as a total display.
Y electrodes are connected to the scan driver 14. The scan driver 14 is equipped with switches 16, and the switches are switched so that scan pulses are applied sequentially during the address period, and in the sustaining discharge period, the odd-numbered Y electrode 12-O is connected to the first Y sustaining circuit 19-O and the even-numbered Y electrode 12-E is connected to the second Y sustaining circuit 19-E. The odd-numbered X electrode 11-O is connected to the first X sustaining circuit 18-O, and the even-numbered X electrode 11-E is connected to the second X sustaining circuit 18-E. The address electrodes 13 are connected to the address driver circuit 17. The image signal processing circuit 21 and the drive control circuit 20 work in the similar manner as explained in FIG. 1.
FIGS. 5A and 5B show drive signals during the sustaining discharge period in the ALIS system. FIG. 5A shows waveforms in the odd field and FIG. 5B shows those in the even field. In the odd field, a voltage Vs is applied to the electrodes Y1 and X2, X1 and Y2 are grounded, and discharge is caused to occur between X1 and Y1, and X2 and Y2, that is, at the odd-numbered display lines. At this time, the voltage difference between Y1 and X2, which form the even-numbered display line, is zero and no discharge is caused to occur. Similarly, in the even field, a voltage Vs is applied to the electrodes X1 and Y2, Y1 and X2 are grounded, and discharge is caused to occur between Y1 and X2, and Y2 and X1, that is, at the even-numbered display lines. The explanation about the drive signals during the reset period and the address period is omitted.
In the power recovery circuit shown in FIG. 3, it is essential to perform recovery and application of power efficiently, and achievement of a high rate of power recovery is expected. The achievement of a high rate of power recovery is influenced by the on/off timing of the output devices 31, 33, 37, and 40. FIGS. 6A and 6B show the influence, FIG. 6A shows a case where the clamp timing is advanced and FIG. 6B shows a case where the clamp timing is delayed.
As explained above, when sustaining pulses are applied, the output device 40 turns on and the power accumulated in the capacitor 39 is supplied to the electrode, and just before the increase of the potential of the electrode is completed, the signal V3 turns to L, the output device 40 turns off, and at the same time, the signal V1 turns to H, the output device 31 turns on, thus the potential of the electrode is clamped to Vs. As shown in FIG. 6A, however, if the output device 31 turns on before the output device 40 turns off, the electrode is connected to the power source of voltage Vs halfway while the potential of the electrode is being raised by the power accumulated in the capacitor 39 because of the turn-on of the output device 31 and, therefore, the power for the rest of the process is supplied from the power source and a part of the power accumulated in the capacitor 39 is wasted and not utilized. Similarly, when the application of sustaining pulses is terminated, if the output device 37 turns on to cause the output device 33 to turn on while the power is being recovered into the capacitor 39, the electrode is clamped to the ground level before the power is recovered sufficiently, therefore the recovery of power is not completed.
Moreover, as shown in FIG. 6B, when the sustaining pulses are applied, if the output device 31 turns on after the output device 40 turns off, the increase of the potential of the electrode by the power accumulated in the capacitor 39 is terminated, and since the output device 31 turns on after the potential of the electrode begins to drop, and the electrode is clamped to the power source of voltage Vs, it is required to raise the dropped potential, resulting in excessive power consumption. Similarly, when the application of the sustaining pulses is terminated, if the output device 33 turns on after the output device 37 turns off, the electrode is clamped to the ground level after the potential, which has been once lowered, begins to rise again, therefore it is required to reduce the increased potential, resulting in excessive power consumption.
As explained above, if the on/off timing of the output devices 31, 33, 37, and 40 in the sustaining circuit is shifted, a problem occurs that the power recovery rate is reduced and the power consumption increases. The on/off timing of output devices 31, 33, 37, and 40 is the timing of the change of the signals V1, V2, V3, and V4 plus delay times of the drive circuits 32, 34, 38, and 41, and further plus delay times of the output devices 31, 33, 37, and 40. Though the timing of change of the signals V1, V2, V3, and V4 can be determined with a comparatively high precision, the delay times of the drive circuits 32, 34, 38, and 41, and those of the output devices 31, 33, 37, and 40 are dispersed depending on variations in characteristics of the devices used. Therefore, the power recovery rate for each PDP apparatus is dispersed, the power recovery rate is lower than that in an ideal case, and a problem occurs that the power consumption increases.
As explained above, if the variations in delay times of the circuit devices cause the shapes and timings of the sustaining pulses to change, the possibility of a malfunction is increased. In general, the difference Δ Vs, which is called the operation margin, of the maximum value Vs (max) and the minimum value Vs (min) in the operational range of the operating voltage Vs is reduced when the delay times of the circuit devices are dispersed and the shapes and timing of the sustaining pulses are altered. This means a deterioration in the operation stability of the apparatus.
In the ALIS system, discharge for light emission does not take place between adjacent electrodes to which the same voltage is applied, respectively. If, however, the timing of application is shifted, a problem may come up that discharge for light emission takes place temporarily at the display lines not for display and wall-charge accumulated during the address period decreases, resulting in an abnormal display. For example, in FIG. 5A, if sustaining pulses are applied to Y1 electrodes and to X2 electrodes after a delay, a situation may occur, temporarily, in which a Y1 electrode is H and at the same time that an X2 electrode is L, and erroneous discharge for light emission may take place between a Y1 electrode and an X2 electrode. Though such erroneous discharge for light emission ceases when sustaining pulses are applied to X2 electrode, the wall-charges of Y1 electrode and X2 electrode decrease and the normal light emission for display may be impeded.
As explained above, there has been a problem that power consumption is increased and a malfunction occurs when the time delays in each circuit device in the sustaining circuit are dispersed and therefore, the on/off timing and the shapes of the sustaining pulses are shifted or changed.